Method and circuit for trimming the internal timing conditions of a semiconductor memory device

ABSTRACT

A method and circuit to trim the internal timing conditions for a semiconductor memory device including a memory matrix and circuit portions for allowing reading of the data stored in the memory matrix wherein such circuit portions include an ATD generator detecting each transition of a plurality of address terminals of the memory device to produce an ATD synchronization signal, a sense amplifier which receives an equalization a signal EQU from a generator activated by the ATD signal, and output buffers enabled by an OUTLATCH signal produced by a generator receiving the ATD signal and the EQU signal. The length of the signals is automatically trimmed according to a corresponding length code contained in a portion of the memory device.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a method and circuit to detect the besttiming conditions for a semiconductor memory device and to trim suchinternal timing.

BACKGROUND OF THE INVENTION

As is well known, semiconductor memory devices such as MaskROM, EPROM,EEPROM, FLASH, SRAM and DRAM have reached such large density andcapacity to store logic information (up to 64 Mbit on a single chip) torequire additional circuit portions for managing and synchronizing thedifferent timing activities of the device. For instance, one of thesecircuit portions is the well known ATD (Address Transition Detection)circuit which is active to synchronize the reading phase of the memorydata. The ATD circuit detects each transition on the address or CEterminals or pins of the memory device and generates a synchronizationsignal which is used for timing many operating functions of the memorydevice. One of these operating functions is the precharge phase of thememory bit lines which must be charged to a predetermined logic level toallow a good conduction of the memory cell storing the data to be read.

For a EPROM device the bit lines are usually precharged to 1 V, whilefor a RAM device the bit lines are usually precharged to 5 V. The timingsetting provided by the ATD circuit is used also to enable the outputdata buffer as soon as the sensing amplifier has detected the logicinformation of the memory cell. Therefore, the detection of an addresstransition, the sensing of the memory cell and the output presentationof the stored data are all operations which must be synchronized and/ordelayed according to the kind and size of the memory device and thetechnology used. The timing schedule of the memory device must bedesigned carefully and this design activity can become very hard for thememory device designer.

Prior Art

A known prior art solution is disclosed in the U.S. Pat. No. 5,444,666assigned to Huyndai. This document discloses a circuit and methodallowing the memory device designer to set up the timing schedule of thedevice. However, this solution has been specifically provided forsynchronizing the redundancy circuit portion of the memory device.

SUMMARY OF THE INVENTION

One object of the present invention is to provide a method and circuitto detect the best timing conditions for a semiconductor memory deviceand to design the memory device according to such best conditions.

Another object of the present invention is automatic trimming of thetiming activity of the memory device, that is: automatically definingthe time intervals of the synchronization signals inside the memorydevice.

A further object of the present invention is to speed up the designphase of the memory device by allowing an automatic timing trimmingwhich optimize the performance of the memory device.

Accordingly, the present invention provides a method to trim theinternal timing conditions for a semiconductor memory device including amemory matrix and circuit portions for allowing reading of the datastored in the memory matrix. The circuit portions include an ATDgenerator detecting each transition of a plurality of address terminalsof the memory device to produce an ATD synchronization signal, a senseamplifier which receives an equalization signal EQU from a generatoractivated by said ATD signal, and output buffers enabled by an OUTLATCHsignal produced by a generator receiving said ATD signal and said EQUsignal. The timing of the signals is automatically trimmed according toa corresponding code contained in the memory device.

The present invention also provides a circuit for detecting the optimaltiming conditions for a semiconductor memory device which comprises amemory matrix and circuit portions for allowing reading of the datastored in the memory matrix. The circuit portions include an ATDgenerator detecting each transition of a plurality of address terminalsof the memory device to produce an ATD synchronization signal, a senseamplifier which receives an equalization signal EQU from a generatoractivated by said ATD signal, and output buffers enabled by an OUTLATCHsignal produced by a generator receiving said ATD signal. The memorydevice includes a latch configured to store the length of the signals soas to automatically trim the signal according to a length code containedin the latch.

Additional objects, advantages, novel features of the present inventionwill become apparent to those skilled in the art from this disclosure,including the following detailed description, as well as by practice ofthe invention. While the invention is described below with reference topreferred embodiment(s), it should be understood that the invention isnot limited thereto. Those of ordinary skill in the art having access tothe teachings herein will recognize additional implementations,modifications, and embodiments, as well as other fields of use, whichare within the scope of the invention as disclosed and claimed hereinand with respect to which the invention could be of significant utility.

BRIEF DESCRIPTION OF THE DRAWINGS

Further features and advantages of the inventive method and circuit willappear from the following description given by way of non-limitingexample with reference to the annexed drawings.

FIG. 1 shows a schematic block view of circuit portions involved in thetiming activity of a semiconductor memory device according to thepresent invention;

FIG. 2 is a timing diagram showing a plurality of different logicsignals having the same time base and which are outstanding during areading cycle of a memory device according to the present invention;

FIG. 3 is a timing diagram showing a plurality of different logicsignals having the same time base and which are outstanding during thesetting up phase of the timing trimming of a memory device according tothe present invention;

FIGS. 4-8 are circuit portions of the memory device according to thepresent invention.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION

In general, the present invention provides a method and circuit to trimthe internal timing conditions for a semiconductor memory device whichcomprises a memory matrix and circuit portions for allowing reading ofthe data stored in the memory matrix.

With reference to FIG. 1, a memory circuit device which is preferablyintegrated on a semiconductor substrate is shown. The memory device 1may be one of the known kind of semiconductor memory chips such as:MaskROM, EPROM, EEPROM, FLASH, SRAM or DRAM. Just as an example, thememory device 1 may be a 1 Mbit Flash EPROM having a memory word ofeight bits.

In any case, the memory device 1 comprises a plurality of input addressbuffers 2 for a corresponding plurality of input address terminals orpins. In this example we will take in consideration a number ofseventeen address terminals and one CE terminal.

All the outputs of the input address buffers 2 are connected to an ATDcircuit generator 8 which detects an ATD pulse from the addressterminals and generates a synchronization signal ATDN which drives allthe other circuit portions involved with the reading phase of the memorydevice. Those circuit portions are: a generator 3 for the equalizationphase of the sense amplifier; a cascode enable generator 4 and anoutlatch generator 5. Each generator 3, 4 or 5 is enabled by the signalATDN to generate local signals EQU, CASCODE ENABLE and OUTLATCHrespectively.

The corresponding outputs of the first two generators 3 and 4 areaddressed to a sense amplifier circuit 6 which includes a senseamplifier for each bit of the memory word; that is the number of senseamplifiers corresponds to the number of the output buffers 7.

The signal EQU is used for precharging the bit lines of the memorydevice and for enabling the equalization phase of the sense amplifiers.On the falling edge of the EQU signal the read data is transferred tothe output buffers. The OUTLATCH signal allows the outputs to keep thedata coming out from the previous reading phase.

Now, according to the present invention a timing trimming of the wholereading phase is provided in order to regulate the length of each phaseof the reading cycle. In other words, the detection of an addresstransition, the sensing of the memory cell and the output presentationof the stored data are all operations which are synchronized accordingto the invention in a trimming way.

The length of the ATD pulse is coded by four bits, three bits fordefining a default or coarse value and one bit for a fine adjustment.The length of the other synchronized signals, such as the EQU signal andthe OUTLATCH signal is coded too. For instance, three bits may be usedto code the length of the EQU signal. Those coding bits may be storedinto a latch which may be obtained from a small portion of the memorydevice.

If the memory device is considered as including a memory matrix of cellseach of which is identified by the intersection of a matrix column witha matrix row, the latch storing the coding of the above synchronizationsignals may be identified by a row portion of the memory matrix.

An example of a possible coding latch according to the invention isshown in FIG. 3. The row addresses A16, A12-A7 as well as the columnaddresses A2-A0 identify a latch memory portion including a specificcode for a different timing trimming.

A latch coding 12 is represented in FIG. 4 to indicate a three bit codeto trim the length of the ATD pulse. The structure of the latch coding12 is shown in FIG. 8 wherein a set of four flip-flop TIMEOFF blocks isprovided for receiving a respective address input signal A12, A11, A10and to store a three bits code for a coarse trimming of the ATD signal.The fourth flip-flop receiving the address input signal A16 is providedfor a finer trimming. A latch coding 13 is also shown in FIG. 4 toindicate a three bit code to trim the length of the equalization signalEQU. A further latch coding 17 is shown in FIG. 4 to indicate a threebit code to trim the length of the OUTLATCH signal. Each latch structurecontains a code which is used to define a different length of thecorresponding timing signal.

The following table 1 reports a possible example of address division fora 1 Mbit memory device in order to trim and set the internal timing ofthe semiconductor memory.

                  TABLE 1                                                         ______________________________________                                        TRIMMING     ADDRESSES    No. of STEPS                                        ______________________________________                                        .sup.T ATD 11                                                                              A16 (fine)   2 (0-1)                                                                           8 (0-7)(coarse)                                 .sup.T EQU            A2-AO                                                                                             8 (0-7)                             .sup.T EVAL          A9-A7                                                                                             8 (0-7)                              ______________________________________                                    

where No. of steps means the number of possible timing combinations and^(T) EVAL is the time interval between the end of the EQU signal and theend of the OUTLATCH signal.

Circuit portions of a circuit according to the present invention areshown in FIGS. 5 6, 7 and 8. Each circuit portion includes a transistorarray in which the transistors are serially and/or parallel connected.

The transistor array represent an equivalent resistance R and, if weconsider such a resistance R in association with a predetermined andfixed load capacitance C of the whole circuit, a variable RC circuit isdefined according to the different series or parallel possibleconfigurations of the transistor array. In other words, by varying theresistance R of the transistor array a corresponding variable RC circuitis obtained as well as a different circuit timing.

For instance, a small array 20 of P-Channel MOS transistors is used tochange the timing of the OUTLATCH signal. Those PMOS transistors areshown in FIG. 7 and are interconnected in a mixed parallel-seriesconfiguration between a first supply voltage, reference Vdd and a groundGND.

FIG. 7 shows a detailed schematic of the inside structure of theOUTLATCH generator 5. A final logic gate 19 receives as inputs the EQUsignal, the ATD signal and a further signal coming out from thetransistor array structure 20. The transistor array structure 20includes a first stage 21 and a second stage 22. More specifically, with21 is indicated a first series or chain of PMOS transistors which isconnected in parallel to a second chain 22 of other PMOS transistorshaving their gate terminals connected to ground.

The first and second chains 21, 22 have different dimensions and set upthe equivalent resistance R of the transistor array 20. The first chain21 comprises five transistors serially connected. The three centraltransistors of this series receive an inverted signal on their gateterminals coming from the OFF output of a corresponding TIMEOFF circuitblock 24. The blocks 24 are flip-flops which form a latch structurereceiving as input a bit of the latch coding 17, and the signals POR andTimeSet.

According to the address input signals A9, A8, A7, and to the resistanceR value determined by the transistor array 20, the timing of theOUTLATCH signal may be determined according of the user needs.

A similar transistor array structure is included also in the ATDgenerator 8 shown in FIG. 8. The detailed structure of the ATD generator8 is shown in FIG. 8.

As may be appreciated, a latch structure comprising four flip-flopTIMEOFF blocks 25, 26, 27, 28 is provided for receiving a respectiveaddress input signal 12, including address input signals A12, A11, A10,and to store a three-bit code for a coarse trimming of the ATD signal.The fourth flip-flop 28 receiving the address input signal A16 isprovided for a finer trimming. A transistor array structure 23, similarto the transistors array 20 of FIG. 7, is used to trim the timing or theATD signal.

Referring back to FIG. 4, a schematic view of a circuit according to thepresent invention is shown for setting up the best timing conditions forthe memory device 1. A time generator 10 is provided inside the memorydevice 1 and comprises a plurality of inputs to receive a logic signalfrom the memory device, as well as the Power On Reset signal, and togenerate as an output a TimeSet signal and a second Signal POR. Thoseoutput signals of the time generator 10 are also applied as inputs ofthe other circuit portions 8, 3 and 5 of the memory device 1.

More specifically, the ATD generator 8 receives as inputs said outputsof the time generator 10 and the logic values contained in the latchcoding 12, that is the code contained in the row addresses A12-A10 ofthe memory device 1.

The logic value (one bit) contained in the row position A16 is alsoaddressed as input of the ATD generator 8.

The ATD generator 8 output is connected to an input of the generator 3of the equalization signal EQU. This generator 3, according to theinvention, receives also as input the logic code 13 contained in thememory column position A2-A0.

The output signal TIMESET of the time generator 10 is also applied tothe EQU generator 3. The output of the ATD generator 8 and the output ofthe EQU generator 3 are applied as inputs of the OUTLATCH generator 5,which receives as well the output signal TIMESET of the time generator10. A further input of the OUTLATCH generator 5 is the coding 17contained in the cells of the memory row A9-A7 which included the threebits for trimming the length of the OUTLATCH output signal.

The detailed structure of the time generator 10 is shown in FIGS. 5, 5Aand 5B. As may be appreciated, the time generator 10 is formed by achain of logic gates which are interconnected to reduce the six inputsof the generator 10 to its output.

A simplified schematic of the circuit structure shown in FIGS. 5A and 5Bis reported in FIG. 5C.

The inside structure of the EQU generator 3 is shown in FIG. 6. The ATDsignal coming from the output of the ATD generator 8 is applied to aCMOS buffer 11 and to the gate terminals of a plurality of NMOStransistors which connect toward ground GND an EQU output line 18. Inthis respect, each NMOS transistor cooperates with a corresponding NMOStransistor connected in series and receiving on its gate terminal asignal coming from the ON output of a TIMEOFF circuit block 14.

Each circuit block 14 is part of a latch structure which receives asinput the bits of the latch coding 13 and the enable signals POR andTIMESET. The latch receives a combination of the address input signalsA2, A1, A0.

Although an embodiment of the present invention has been shown anddescribed in detail herein, along with certain variants thereof, manyother varied embodiments that incorporate the teachings of the inventionmay be easily constructed by those skilled in the art. Accordingly, thepresent invention is not intended to be limited to the specific form setforth herein, but on the contrary, it is intended to cover suchalternatives, modifications, and equivalents, as can be reasonablyincluded within the spirit and scope of the invention.

We claim:
 1. A method for controlling the internal timing conditions fora semiconductor memory device including a memory matrix, said methodcomprising the steps of:detecting each transition of a plurality ofaddress terminals of the semiconductor memory device; generating anaddress transition detection (ATD) synchronization signal in response tothe transition detecting; generating an equalization (EOU) signalactivated by said ATD signal; generating an OUTLATCH signal activated bysaid ATD signal and said EQU signal to enable an output buffer circuitryof the semiconductor memory device; and automatically trimming thetiming of said ATD, EQU and OUTLATCH signals according to acorresponding code contained in said semiconductor memory device.
 2. Themethod according to claim 1, wherein the timing of said ATD, EQU andOUTLATCH signals are each regulated by a distinct transistor arrayhaving a variable equivalent resistance controlled by the correspondingcode.
 3. A circuit for detecting the optimal timing conditions for asemiconductor memory device which comprises a memory matrix, a pluralityof address input signals and circuit portions for allowing reading ofthe data stored in the memory matrix, the circuit comprising:an addresstransition detection (ATD) generator detecting each transition of aplurality of address input signals of the semiconductor memory device toproduce an ATD synchronization signal; an equalization generatoractivated by said ATD synchronization signal for generating anequalization signal for equalizing a sense amplifier in thesemiconductor memory device; an enabling generator receiving said ATDsignal and generating an enable signal for enabling an output buffercircuitry of the semiconductor memory device; and wherein saidsemiconductor memory device includes a latch configured to store timingdata therein representing one or more pulse width values forprogrammably trimming the ATD, equalization and enable signals.
 4. Thecircuit according to claim 3, wherein said latch includes an array offlip-flops, each of which receives an address input signal correspondingto a distinct circuit portion of the memory device.
 5. A device forcontrolling control signals internal to a semiconductor memory devicehaving input address terminals, a memory array and an output buffer,comprising:detecting circuitry for detecting an edge transitionappearing on at least one of the input address terminals; and addresspulse circuitry for generating an address transition detection (ATD)pulse signal responsive to the detecting circuitry, a pulse width of theATD pulse signal being programmable.
 6. The device of claim 5, furtherincluding:conditioning pulse circuitry for generating a conditioningpulse signal for conditioning circuitry associated with a bit line inthe memory array, a pulse width of the conditioning pulse signal beingprogrammable.
 7. The device of claim 6, wherein:the conditioning pulsecircuitry is responsive to the address pulse circuitry.
 8. The device ofclaim 6, further including:enable pulse circuitry for generating anenable pulse signal for enabling the output buffer of the semiconductormemory device, a pulse width of the enable pulse signal beingprogrammable.
 9. The device of claim 8, wherein:the enable pulsecircuitry is responsive to the conditioning pulse circuitry.
 10. Thedevice of claim 8, further including:storage circuitry for storing aplurality of codes, each code corresponding to a distinct one of theaddress pulse circuitry, the conditioning pulse circuitry and the enablepulse circuitry for determining a pulse width generated thereby.
 11. Thedevice of claim 10, wherein:the address pulse circuitry, theconditioning pulse circuitry and the enable pulse circuitry eachincludes a transistor array; and transistors in each transistor arrayare activated based upon the code corresponding thereto.
 12. A circuitfor controlling the generation of control signals internal to asemiconductor memory device having a plurality of address input signals,comprising:first circuitry for storing one or more codes in thesemiconductor memory device; second circuitry for detecting an edgetransition appearing on one or more of the address input signals; andthird circuitry, responsive to the second circuitry, for generating anaddress transition detect (ATD) pulse signal, timing characteristics ofthe ATD pulse being based upon the one or more codes stored by the firstcircuitry.
 13. The circuit of claim 12, wherein:a timing delay betweenthe detection of the address input signal edge transition and an edge ofthe ATD pulse signal is based upon a first code stored by the firstcircuitry.
 14. The circuit of claim 13, wherein:at least one first codesignal corresponding to the first code drives a control electrode of atleast one transistor within the third circuitry for effecting an edgetransition delay of the ATD pulse signal.
 15. The circuit of claim 12,further including:fourth circuitry, responsive to the third circuitry,for generating a conditioning pulse signal for conditioning at least onebit line in the memory array, timing characteristics of the conditioningpulse signal being based upon the one or more stored codes.
 16. Thecircuit of claim 15, wherein:the third circuitry generates the ATD pulsesignal having a leading edge and a trailing edge; and the fourthcircuitry generates the conditioning pulse signal having a leading edgeand a trailing edge, wherein the timing delay between the trailing edgeof the ATD pulse signal and the trailing edge of the conditioning pulsesignal is based upon a first code stored by the first circuitry.
 17. Thecircuit of claim 15, further including:fifth circuitry, responsive tothe fourth circuitry, for generating an enable pulse signal for enablingoutput buffer circuitry of the semiconductor memory device, timingcharacteristics of the enable pulse signal being based upon the one ormore stored codes.
 18. The circuit of claim 17, wherein:the fourthcircuitry generates the conditioning pulse signal having a leading edgeand a trailing edge; the fifth circuitry generates the enable pulsesignal having a leading edge and a trailing edge, wherein the timingdelay between the trailing edge of the conditioning pulse signal and thetrailing edge of the enable pulse signal is based upon a first codestored by the first circuitry.
 19. The circuit of claim 17, wherein:thethird circuitry, fourth circuitry and fifth circuitry each includes atransistor array; and the first circuitry stores a plurality of codes inthe semiconductor memory device, each code activating transistors of adistinct transistor array for effecting an edge transition time of theoutput thereof.
 20. A method of controlling the generation of controlsignals internal to a semiconductor memory device, comprising the stepsof:storing one or more codes in the semiconductor memory device;detecting an edge transition appearing on one or more address inputsignals; and generating an address transition detect (ATD) pulse signal,timing characteristics of the ATD pulse being based upon the one or morecodes stored in the step of storing.
 21. The method of claim 20,wherein:the generating step includes the step of delaying the generationof an edge of the ATD pulse signal by an amount that is based upon acode stored during the step of storing.
 22. The method of claim 20,further including the step of:generating a conditioning pulse signal forconditioning at least one bit line in the semiconductor memory device,based upon the one or more codes stored during the step of storing. 23.The method of claim 20, wherein:the step of generating the conditioningpulse signal includes the step of delaying the generation of an edge ofthe conditioning pulse signal relative to the generation of acorresponding edge of the ATD pulse signal by an amount that is basedupon the one or more codes stored during the step of storing.
 24. Themethod of claim 22, further including the step of:generating an enablepulse signal for enabling an output buffer in the semiconductor memorydevice, based upon the one or more codes stored during the step ofstoring.
 25. The method of claim 24, wherein:the step of generating theenable pulse signal includes the step of delaying the generation of anedge of the enable pulse signal relative to the generation of acorresponding edge of the conditioning pulse signal by an amount that isbased upon the one or more codes stored during the step of storing. 26.The method of claim 24, wherein:the step of storing comprises the stepof individually storing a plurality of codes in the semiconductor memorydevice, each code indicating a timing delay utilized during thegeneration of a distinct one of the ATD pulse signal, the conditioningpulse signal and the enable pulse signal.
 27. The method of claim 20,further comprising the steps of:replacing the stored one or more codesin the semiconductor memory device with one or more replacement codes;and repeating the step of generating the ATD pulse signal, timingcharacteristics of the ATD pulse signal being based upon the one or morereplacement codes.